[…]
“AAJ1. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error
[…]
“AAJ1 – No Fix”
[…]

Of course the final impact e.g incorrect results etc. etc. is not documented at all.

the target of this blog and upcoming site is to offer insight views’n’opinions, and this story was just that.

I’ve read the whole document and saw references to an old document which resulted in that old story on the INQ. Woodcrest/Conroe suffered from instabilities and prior to launch, Intel lost the LLNB contract due to instabilities and higher reject rate. The consequence of that bug (and RAID controller bug) caused Intel to lose the “technology partner” status with GAO and subsequently, AMD walked right in with its CPUs, scoring major wins in US Supercomputing space.

One nasty scaling benchmark from Lawrence Berkeley National Labs also killed off Woodcrest/Conroe architecture… and seeing that bug making reappearance in Core i7 didn’t make any sense.

After reading the piece, I decided to wait for Intel’s answer, since the situation was confusing. This meant sitting on a story, but it is better to offer a good answer than a half-baked one.

Not defending anyone, it is hard being editor-in-chief, and that is something I am taking a role starting in weeks from now. But I will stride to offer complete information, no matter what. And I will do the same to my colleagues which are joining the project.

This was a neat story to break, but it was just too murky. If Nehalem was causing instabilities, that would be “story of the year”.

I have sent off an e-mail to Intel to get clarification but now I feel that it is not needed due to this well written article that lay before us.

To make a long story short a moderator at EVGA “RussianHAXOR” pointed another member “AuDioFreaK39” to this article who intern pointed the rest of us over.

Thank you for real, true and honest reporting.
Johnathan (UserX)