here’s a question. What would you rather have: Grumman and Airbus building tankers for US military and creating 50,000+ jobs in AL plus 30,000 in other states or American Boeing offshoring tens of thousands of jobs to Japan, Italy and other places?

If you want to put a nationalistic spin on it…. that is.

Regards,

Theo

“There were significant changes in the way how a fab is being designed and case is closed there. Ecological, space-wise, construction wise. That Fab is the first APM 4.0 Fab, so we’ll see how it will go.”

The case is not closed – just because changes were made, doesn’t make them unique or native or in anyway tied specifically to 22nm process technology. My question: is any of this specific to 22nm to make F4X a “native” 22nm fab? I’m still trying to understand your original blog that the NY fab is a native 22m factory

Basically what I’m asking is APM 4.0 specific to 22nm technology or is it more a matter of that technology being ready to be implemented when the fab happens to be starting up? (or in other words if F4x turned out to be a 32nm fab for whatever reasons, would APM 4.0 not be implemented?). As for ecological, again I would like to understand how the improvements are specific to 22nm, or are they merely fab improvements that just happen to intercept the timing and are ready to implement in the NY fab?

I’m not questioning that these improvement are real. I’m not questioning whether they will be done in the NY fab or whether that fab will be different. I’m questioning your characterization of the fab as “native 22nm” and implying (or perhaps I’m just misreading), that something is somehow unique or specifically designed to 22nm. I would propose that these are merely technologies that are ready to go when the NY fab is being built and would have been implemented regardless of what technology node that fab would be running (and thus there is nothing “native 22nm” about the fab). Do you disagree?

And yes I do think you were misleading your readers on the real fab capacity of AMD in 2012… perhaps I should not have punctuated it with an “!” and I certainly could have worded it more politely, but AMD’s own foils contradict your assessment and frankly I’m more inclined to trust the CEO of AMD’s new foundry then your estimates. This is not meant to be an attack, I just think AMD has a better understanding of it’s capacity then you do.

They obviously could have been wrong at the analyst day 2-3 months ago, or plans could have been changed – but in the absence of any other data, I’m not sure why AMD’s presentation should be dismissed and your estimate is more accurate. I would honestly like to hear why – do you have some knowledge, even if you can’t share it, that their plans have changed since the Nov presentation?

According to AMD’s roadmaps, first 32nm (first 32nm is bulk, followed by SOI HKMG) chip will be Radeon GPU (tapeout in late 09, rollout in 2010).

2009 will see 2nd wave of 45nm CPUs, probably a new and improved revision (D?) and this includes chipset side (800 series should be built in 45nm instead of 55nm).

AMD’s 32nm CPU’s won’t be ready before Computex 2010. Yes, K10 architecture will see 32nm parts, unless Bulldozer pulls a small miracle and comes out six-months to one full year early.

Everybody is entitled to his own opinion. I listened to every AMD’s quarterly since July ’05, and I have my notes. In those notes, AMD produced large number of discrepancies and quite honestly, wrong information. The company wasn’t honest about the reasons for the 65nm delay (it wasn’t technical), why 90nm was improved and what were the issues with 45nm ($$$ for tools). Can AMD pull it through on the 22nm node?

In Joe’s interesting dissection of my article and comments afterwards, I was called quite interesting names, thus I’ll refrain from further discussion. The fact that I did not delete his posts means I am leaving them as “food for thought”, but I am not going to address them until their MO is changed to a decent level of communication.

Again, I will not go into discussion with the person that stated this: “Stop misleading the readers and making this sound like some novel approach to 22nm or fab design!”

Without knowing what were the topics of my discussions on the subject of NY Fab were (I don’t exactly recall how I mentioned or assumed that AMD is making something”novel”). There were significant changes in the way how a fab is being designed and case is closed there. Ecological, space-wise, construction wise. That Fab is the first APM 4.0 Fab, so we’ll see how it will go.

Unless real fab architects wants to disclose building plans and provisions in a public forum or via e-mail, there is nothing to discuss. Upcoming site will feature some interesting interviews, so I’ll leave the room for real experts on the subject.

There are 3 different processes for 32nm, and just the low powered one is ready for an early 2010. The other 2 can just yield chips in the second semester, which is a bit late.

Sorry – wasn’t suggesting you were responsible for the table (or brought it up)- some other commenter asked how real it might be. I think given the table has a “C4″ revision in Q4’10 shows how authentic (or inauthentic) it is. It appears whoever made the table just made up the revisions #’s and if they made that up, along with a change in the clock scheme moving to increments of 5 in the model #, suggests the table is more about hope and extrapolation as opposed to some inside knowledge.

Theo – you didn’t comment about Joe’s link about the AMD analyst day foils. It seems he brought up some reasonable information which contradict some of your comments and some of your analysis about overall AMD capacity capability in the original article. I have to agree almost everything you assume is the absolute best case and some of your assumptions on ramp rates of a factory are not reasonable (using the ramp of a 200mm fab on a known technology nodet o project the ramp of a 300mm fab on a new technology node is not reasonable as there are significant differences)

When it comes to revision numbers, don’t think that C revision is going to stay around forever. AMD introduced different revisions under the same product family and manufacturing process in the past.

I have given my view on 3.1/3.3 and 3.5/3.6 as maximums that AMD can reach on air. My assumption on 3.5-4.0 GHz on air in 2010 is tied to the introduction of 32nm HKMG SiGe process over at AMD, and of course, that is if K10.5 receives a die-shrink, rather than some architectural changes.

Personally, AMD needs to look somewhere else for performance boost, and that “somewhere else” is the fact that their CPU cores work asymmetrically to the MemCtr/L3 cache. That is the battle AMD is facing and main reason why their CPUs are not exactly… that great. Async cache is way to performance doomsday, and that was proven in the past, present and the future.

When it comes to manufacturing debate, I think I will refrain from finishing articles at 2-3AM and publishing them, since during re-read I am noticing that I wasn’t as clear as I wanted to be. E.g. think one thing, write another.

To be perfectly clear, I know how manufacturing process is measured (50% of DRAM cell pitch, half-side pitch etc.), but there is certain thing called allowances. During my visit to Fab30/36 complex in 2006, we were explained that by working hard on optimizing the 90nm process, with VP of Manufacturing bragging that the engineers managed to bring the spacing close to 65nm specifications (it was explicitly mentioned what lengths were allowed by 65nm and 90nm definitiions and Fab36 was able to pull 65nm-like values on 90nm process, 13th generation transistor. 9th Gen transistor was the base for 65nm process… and again, these statements are taken out of context).

And yes, spacing doesn’t dictate speed/performance. But it is interesting that discussion about Fabs turned into “Phenom II kicking 3.5G this year”. Kinda didn’t noticed when it turned into that direction.

Well, I only have time for this blog in the evenings, given that during the day I am occupied with the preparations for the launch of the new site.

That’s my point… the table seems to have extrapolated clock speeds by seeing how many #’s can we get from 940/945 to 995. To maximize the clock gains, increments of 5 were used, which goes against AMD’s current naming convention (a jump of 10 is 100MHz for the X4 PII).

And I’m not doubting AMD process improvements – I’m doubting the rather suspect (and I believe made up) use of C3, C4 revisions in the table. As even you noted, a # change on a revision is often a design change whereas a significant process improvement would likely have a revision with a letter change. I think the table is just a made up extrapolation from someone, based on these 2 items.

The other inherent assumption is there is nothing on the architecture preventing the clock gains. There may be critical speed paths other than the transistor, which limit speed. Simply being able to overclock doesnot mean these speedpaths are addressable for stock products (we have seen this on Intel products as well). So for those saying – well I can OC to 3.6-3.8GHz on reasonable voltages, therefore we should eventually see these stock parts over time, it doesn’t hold.

Theo – the spacing between transistors has nothing to do with the name of the technology node (90nm doesn’t mean 90nm spacing between transistors). Nor does the spacing between transistors dictate speed/performance.

AMD launched Dragon platform in two waves, with AM2+ and soon-to-launch AM3 processors. Dragon is combination of AM2+ or AM3 processor, 790 series chipset and 55nm GPUs (Radeon 4800). Second platform to launch in 2009 is Leo, with AM3 processors, 890 chipset and 40nm GPUs (Radeon 5800). Launch of Leo platform will be in tune with AM3 Black Edition processors of higher clocks that are planned for February.

The table clearly stated 3.2, 3.4 GHz in Q2’09. With the apperance of 3.1 GHz processor, all of a sudden there is talk about 3.5 GHz. I am expecting that AMD will launch 3.1 and 3.3 GHz for Leo platform. By the end of the year, we should see 3.5 and 3.6 GHz.

Phyton platform is based on 900-series chipsets, but you won’t see that before 2010. Phyton was supposed to launch in conjuction with M-SPACE processors (e.g. Bulldozer), but with Bulldozer now stuck in 2011, two-years off target, I suspect that you will see 3.5-4.0 GHz processors in 2010.

RE: Frank – Frank, AMD improves its manufacturing process in “generations”. For instance, 90nm process lived through four generations (and ended up with 70nm spacing between transistors), 65nm had just two “generations”. It is too early to say what’s going on with 45nm, but I heard some promising step ups and they already went through two “generations”.

This should enable those miracle cores of the past (Winchester etc.), e.g. optimized design. Barcelona really wasn’t a good example, since it was broken in B0, B1 and B2 silicon, so they had to fix it for B3.

9×0 vs 9×5 is difference between AM2 and AM3. IMO, that was nothing else but “we have to launch Dragon at CES” move, since Dragon platform (DDR3) is three months late (Oct 08 anyone?). Thus, 920 and 940 came to life.

I don’t see any viable reason for those two to exist other than “we could not make DDR3 platform on time”, since all AM3 CPUs should be compatible with AM2/AM2+ motherboards.

I assume the revision #’s have been put in the chart for a reason? If they have, then making up the revision # (which appears to be the case) or putting in placeholders, calls into question the veracity of this table.

Does the perfect spacing of 0.1GHz per quarter for 5 consecutive quarters also seem a little suspect?

Finally, wasn’t amd using the 9×0 vs 9×5 numbering scheme to denote AM2+ vs AM3 models for the PII X4? Or is the table just suggesting they abandon that after the 940?

I listed them in the first post of this forum.

http://www.amdzone.com/phpbb3/viewtopic.php?f=52&t=136040

Both of them agree on 3.5GHz in 2009.

So, AMD’s desktop CPU’s are totaly lost in 2010? Or do you think they can achieve 4GHz?

See page 16 from Doug Grose and the capacity plans. Some things of note:

2012 show MINIMAL capacity from the NY fab… eyeballing it, it looks like 20-25% built out (This debunks your myth of full build out in year if it is starting up late 2011 or early 2012)

2012 total wafer starts is ~650,000 wafers, or just over 50,000 wafers/month (This debunks your myth of 75K WSPM and your estimate was just under 1 million in 2012)

Note – this is the same presentation that contains the slides you CHOSE to present in your blog article… either you chose not to read the whole thing, were separately given some of the slides by whoever your sources are, or you deliberately omitted the stuff that conflicts with your “analysis”.

In any event, are things clearer now?

You need to stop interpreting things… a fab is not ‘natively’ designed to handle SiGe or HIGH K or whatever… this merely means different tools, chemical are used in the fab. Whoever “explained it to you” is exploiting your lack of knowledge. The fab is a fab…. it can accept a high K tool or a SiO2 or a tool that can handle SOI wafers (which by the way is any 300mm tool).

What you are essentially saying is they are reserving some ‘swing’ space (sorry this is an industry term essentially meaning fungible or extra space)…. there is nothing “designed” into the fab. This is simply basic fab and capacity planning that goes on at TSMC, Intel or any other fab in the world. Stop misleading the readers and making this sound like some novel approach to 22nm or fab design!

And for you to simply count # of fabs saying intel needs 14 to supply 80% and AMD needs 1 for 20% is completely insane. Does AMD produce chipsets in house? Do they produce wireless chips? Do they produce memory (NOR)? Are the fab sizes all equivalent in terms of capacity and wafer sizes? (No) Do you consider Chartered contribution to capacity for AMD? Have you factored in relative die size of the products? How about the relative mix of quad core vs dual core vs single core?

Me thinks you are simply trying to justify AMD, not present any sort of knowledgeable or objective form of analysis. If I want that I’ll go to AMDzone.

“It happened before (Fab30), it can happen again.”

Fab 30 was 200mm, those tools install quicker, qualify quicker and oh by the way that was done on a process that was already qualified and certified (where as the NY fab apparently will be the first 22nm process startup for AMD). Additionally the cycle time on lots for that process flow is different from today (meaning today they take longer to move through the fab, which lengthens tool qualification time, process certification times and thue ramp speed). You using F30 as justification for a <1 year ramp is all anyone needs to know about your level of knowledge of this industry.

I appreciate your sources and don’t doubt them, but honestly you do not appear to have the background to analyze them correctly and are producing wrong or flawed conclusions.

Finally your designed for 20K got tro 30K is nice, but that is clearly taken from the AMD analyst days and I’m not sure if you understand how they did it. The move from 20K to 25 K was real and very good (though a 25% increase in capacit is not unheard for a factory over it’s lifetime as tools get improved over time and run faster, have better availability/utilization, etc. The final move from ~25K to 30K was largely done by stuffing support equipment into the F36 shell. While I applaud AMD for doing this and it was a very creative and highly useful solution, it is not something “special” or even sustainable – they were able to do it because F36 was not built out, not because of some remarkable design or F30. If AMD built an annex onto the side of the fab they could accomplish a similar thing – though I probably wouldn’t call it soemthing special about the original Fab, I’d call it using additional space.

But in all honesty, when 32nm Westmere comes along, AMD will have a tough time.

The company management made their architectural decisions, they were wrong and they now need to live until K11 comes along with completely new architecture. So, Sandy Bridge vs. Bulldozer and Bobcat.

Not sure what sense it will make, but AMD is definitely planning to launch higher-clocked CPUs. They will introduce new models as they improve the manufacturing process, and keep the higher clocks in their 95/125W TDP envelopes.