BSN* was one of the few reporters who was invited to San Francisco for Intel’s press conference on their eight-core Nehalem-EX server roadmap. The Nehalem-EX processor will feature up to eight cores inside a single chip supporting 16 threads and 24 MB of cache for four-socket and larger servers. The two-socket version was announced in late March.
The chip is promised to arrive in Q4 2009. Nehalem-EX will add new reliability, availability and serviceability (RAS) features traditionally found in the company’s Intel Itanium processor family, such as the Machine Check Architecture (MCA) recovery. Together with new levels of performance, Intel forecast that both high-end processors should speed the move away from more expensive, proprietary RISC-processor based systems. Boyd Davis, general manager of Intel’s server platforms marketing group, said that MCA recovery will detect and fix errors that could otherwise cause systems to crash.
Davis said that the chip will be able to set system errors originating in the CPU or system memory, and work with the operating system to correct them. He said that would help make systems more fault tolerant and provide greater uptime. This level of error correction in the Nehalem-EX is a step away from Intel’s marketing strategy. Previously only the Itanium servers had this level of error correction. Davis brushed aside the question that the Nehalem-EX processor might take away sales from its more expensive Itanium servers.
Xeon 7500s were once known by the code-name "Beckton". When they come to market and they will have over 2.3 billion transistors and will be implemented in Intel’s 45 nanometer High-K metal gate technology. This is the same process that Intel used to make the "Nehalem-EP" chips used for two-socket servers that were launched back on March 30. Given that the 32nm process will be available by the time Xeon 7500 debuts, it looks like Intel is happy with the maturity and yields on a current 45nm process nodes and confident that the yields for a single-die approach with eight cores.
Intel’s press release and slides claim that the Nehalem-EX will offer up to nine times the memory bandwidth of the previous generation Intel Xeon 7400 platform. Nehalem-EX will also double the memory capacity with up to 16 memory slots per processor socket, and offer high-bandwidth QuickPath interconnect links.
Alex Yost, vice president in charge of IBM’s System X and BladeCenter business, demoed their own fifth-generation eX5 technology version of the Nehalem-EX which is also capable of 8 cores and 16 threads. It will appear in servers with up to 8 processor sockets. A fully populated eX5 Nehalem-EX server will include 64 cores and support up to 128 threads. IBM claimed over ten first places in various server benchmark testings. The weak part of the conference was the fact that we were not privileged to watch at their server operating, because it was located in another room. For a brief period of time we did see on-screen, a static benchmark showing what we were told was the operating server.
A no-name four CPU server chassis mockup with eight memory modules was in the lobby. It was a four-socket Nehalem-EX box featuring 32 processor cores, 64 threads, and used 8 GB DDR3 DIMMs. It could support as much as 512 GB of main memory. Without any special chipset, a server can expand to double that – 64 cores, 128 threads, and 1 TB of memory.
All this is without anything other than Intel’s chips and the Boxboro-EX chipset.The Nehalem-EX will include separate buffered memory chips that can temporarily store data alongside the main memory for faster execution. This means less expensive unbuffered DDR 3 DIMM’s will be used. Davis was asked about the large heatsinks on the memory modules. He said they were for testing purposes and would probably be changed by the OEM’s when they start shipping their own versions of the Nehalem-EX servers.
Intel’s roadmap presentation just happens to be a week before AMD is rumored to announce at Computex that they are going to ship their six-core Istanbul chips. The press conference was somewhat of a polite way for Intel to take some of the limelight away from anything AMD does next week in Taiwan. Originally, Intel planned this event as a pre-emptive strike for all those Opteron benchmarks that were supposed to come out on the May 27th, but AMD pushed back the NDA and this and the next weeks’ HPC-segment limelight spot officially belong to Xeon 7500 e.g. Nehalem-EX.