According to DigiTimes, quoting TSMC?s R&D boss Shang-yi Chiang, TSMC will begin volume production on 14nm in 2015.
Intel has been shipping in production volumes on its 32nm process since 2009 and originally intended to start shipping 22nm process this year. However, there are rumors that the 22nm node will be delayed. DigiTimes said earlier this month: "Intel has recently decided to delay its Ivy Bridge platform launch from the end of 2011 to March 2012…" – and the server "Romley" platform is plagued not just by issues with 22nm process, but with chipset issues as well.
Intel?s technology road map in late spring called for production on 14nm node in 2013 and to begin 10nm node production in 2015. It will be interesting to see next week at IDF Fall San Francisco what their roadmap will show now.
The DigiTimes article says TSMC?s Chiang also expects to be manufacturing on 450mm (18 inch diameter) wafers in 2015.
During the GlobalFoundries Technology Conference (GTC) at the end of last month, Gregg Bartlett, senior VP of technology, presented the company’s latest technology roadmap.
GlobalFoundries Roadmap: 28nm-SHP in 2012, 20nm-SHP in 2014
GlobalFoundries plans to introduce 20nm technology for lower-power applications, including networking applications and wireless and mobile computing in 2013, followed by 20nm for high performance computing in 2014. In other words, GlobalFoundries should be able to make the kind of CPUs that AMD designs for desktops and laptops on 28nm next year, and on 20nm in 2014. That is, if AMD’s plans actually go exactly like the rumors to analyst keep claiming the will accomplish on time deliveries.
Bartlett showed a slide of a roadmap with GlobalFoundries moving from 32nm to 14nm node. However, projected dates for each node’s downsizing were missing.
Innovations beyond 20nm at GlobalFoundries: 3D integration and Source Mask Optimization at 22/20nm node, Extreme Ultraviolet and Non-Planar Structures (FinFET), and Fully Depleted ETSOI at 16nm and 14nm
An interesting sidelight during GTC was BSN’s conversation with Paul Boudre, COO of Soitec, France.
Boudre outlined more of Soitec’s roadmap which was first discussed by Steve Longoria, Soitec’s Senior VP, global strategic business development, at Semicon West in July. Longoria said for nodes smaller than 20nm the industry is going to either 3D Tri-gate FinFET structure [Intel] or fully-depleted planar Silicon-On-Insulator (FDSOI), as used by semiconductor alliance between IBM, Samsung, GlobalFoundries and ST Microelectronics. Soitec provides wafers for both approaches.
There is a new process being developed by the EV Group (EVG), a leading supplier of wafer bonding and lithography equipment. They have unveiled the semiconductor industry’s first bonding system for 450mm wafers manufactured from silicon-on-insulator (SOI) substrates. These new machines will produce 450mm SOI wafers that will then be used to make chips.
The new EVG850SOI/450-mm wafer bonding system is a fully automated tool for production-level fabrication of SOI wafers. The EVG850SOI/450 mm consists of two process modules: a cleaning module for cleaning and pre-conditioning of wafers before wafer bonding, and an SOI pre-bonding module. In the pre-bonding module, the two silicon wafers are joined together either in a vacuum or in an atmospheric chamber. The tool is equipped with state-of-the-art 450mm load ports and front opening unified pods (FOUPs).
Boudre said "Soitec is willing to position (ourselves) in the 450mm transition. With the launch of this new system, EV Group is offering the semiconductor industry a highly viable solution to ease the transition to 450mm wafers. With our well established SOI material playing an increasingly greater role in fabricating next-generation ICs, we look forward to working with EVG to ensure this new system is ready to enter mainstream production in a timely fashion."
TSMC and Intel have not made any announcements about using SOI, even though both companies have publicly demonstrated technologies manufactured using SOI, such as TSMC’s 65nm semiconductors or Intel’s innovative Silicon Photonics concept which should become a reality circa 2015-16.
At GTC last month, GlobalFoundries management was not forthcoming about their plans for their transition from 300mm (12 inch diameter) to 450mm (18 inch diameter). GlobalFoundries’ Fab 8 in Malta, New York, has over 100,000 square feet on clean room space which is installing production equipment as this is written. There is space on the property at Malta, New York, for another fab of equal size to Fab 8. Fab 8 is designed to handle 14nm node wafers.
The rumors in the SOI equipment manufacturers? community is that Samsung will be the first to have the 14nm, FDSOI, 450mm wafers in volume production. Clearly, the coming year will be one of many more rumors about this leap forward in wafer technology.