In January AMD launched the Kaveri APU, which is the first APU product with HSA support. While until today only two desktop SKUs have been launched, with more planned down the road as well as a full notebook lineup, AMD is already working hard on the next generation APU. The new chip’s codename is Carrizo and I had the chance to look at a document aimed at developers "Preliminary BIOS and Kernel Developer?s Guide (BKDG) for AMD Family 15h Models 60h-6Fh Processors?, which documents some of the new features of this APU.
The CPU cores will be upgraded from Steamroller to Excavator. Thanks to a patch AMD submitted to the GCC project last September, we know that Excavator will add support for AVX2, BMI2, MOVBE and RDRAND instruction set extensions. Except for the TSX extensions found on select models, this brings the core to feature parity with Haswell. Other than that not much is known about any enhancements Excavator will bring to the table. The document I have seen is vague and only mentions "IPC/Architectural changes" which alludes to the optimizations AMD has planned for Excavator back when the roadmap for the Bulldozer architecture was laid out. No further changes regarding cache sizes are mentioned.
The GPU of Carrizo will stay largely the same as in Kaveri. The document mentions "Volcanic Island tiles", which technically Kaveri also has as it is architecturally on the same level as the Hawaii GPU. While I don’t want to preclude that it contains architectural tweaks not mentioned in this document, for now no information on any such enhancements is known. It is not mentioned whether the number of CUs will change. Given we know that Carrizo will be manufactured at the 28nm node, albeit a different process than Kaveri, it is unlikely AMD adds more compute units to the GPU.
The memory controller of Carrizo will feature support for both DDR3 and DDR4 memory technologies. On the DDR3 side of things memory support looks largely unchanged from Kaveri. The only addition seems to be support for Registered DIMMs, which is probably reserved for the server version called Toronto. Aside from the mention of DDR4 support, the details for DDR4 operation are absent from the document. The maximum memory frequency is still 2400MHz as it was on Kaveri. I wonder if this is also the maximum DDR4 frequency supported or whether the lack of DDR4 documentation also caused a lack of information here. After all, the currently stated speeds of DDR4 as we know it on Intel’s chipsets is 2133 MT/s (or MHz) and that could be why we don’t see anything about DDR4 speeds.
One of the main innovations of Carrizo is the integrated Fusion Controller Hub (FCH). It will feature two SATA 6Gb/s ports, four USB 3.0 ports and eight USB 2.0 ports. Furthermore, two UART and four I2C interfaces as well as a SD Card interface will be provided. This functionality will only be available on Carrizo for the FP4 package, which is a BGA package soldered to the board aimed at notebooks. Speaking of packages, there is another BGA package called SP2 mentioned in the document. Since leaked roadmaps mentioned a server version called Toronto in a BGA package, it might be this one. The document lists some minor difference in terms of maximum supported memory frequencies for SP2 (i.e. 2133 maximum for SODIMMs with a single populated channel with dual rank modules on SP2 vs 1866 on FP4) and additional memory technologies (RDIMM, LRDIMM ? i.e. Registered DIMMs) supported on SP2.
On desktops Carrizo will drop into the known FM2+ socket and the integrated FCH will be disabled and the external FCH of the board used. This is an understandable tradeoff to avoid changing the motherboard infrastructure again. While some users might dislike the fact, that there is dormant silicon in AMDs upcoming APU for the desktop, the functionality is not sufficient to satisfy the needs of desktop users. If anything, it would be a nice to have addon to the current standalone FCH features. On the laptop side the connectivity should be sufficient though.This innovation also helps drive down the power consumption and thus increase battery life so we applaud AMD for taking the next logical step in SoC integration for the mainstream platform. It also reduces complexity on the logic board level, thus allowing cost savings and potentially sleeker designs. Currently similar functionality is only found in Kabini and Temash-SoCs aimed at tablets and entry-level PCs/notebooks.
Given that Carrizo also features a DDR3 memory controller, we have no reason to believe that the new core wont work in existing mainboards with a BIOS update. However, for now there is no guarantee this will work out either. We have to wait for an official confirmation from AMD at a later date, but for now things are looking good, given AMDs past track record with socket changes. In order to use DDR4 memory, new mainboards will be required that will be incompatible with current FM2/FM2+ APUs lacking DDR4 support. Not to mention the fact that DDR4 will have different slotting and electrical constraints.
The PCI-Express connectivity got a slight update as well. While Kaveri already had PCIe 3.0 for discrete graphics connectivity, the general purpose lanes were PCIe 2.0. In Carrizo all PCIe lanes are version 3.0, thus providing more bandwidth for addon devices. The PCI Express complex reveals another tradeoff AMD had to make. Unless there is a mistake in the document due to it’s early state, AMD considerably reduced the amount of available PCIe lanes, from 24 total to 16 total. The discrete graphics connectivity only features 8 lanes that can be split into two x4 links. The general purpose core features 4 lanes that can be split into up to four x1 links, two x2 links, a combination of x1 and x2 links or a single x4 link. On the desktop version four additional lanes are available for the UMI interface to the FCH. On the BGA versions these lanes are not available, as the internal FCH is connected to these ports. It is unclear yet, why the graphics connectivity was chopped down and it is an aspect I will try to shed some light on at a later date.
For the server variant called Toronto the APU also has new RAS features in store, namely ECC memory support and support for data poisoning. This feature allows continued operation in the case of some errors that can’t be corrected and can mark the associated memory as poisoned. Only when the poisoned data is accessed a machine check exception is raised, which allows software to react to the error condition. Data poisoning is supported when ECC RAM is used, but will also cover caches and data from I/O links.
Overall, the information I was able to dig up gives us a better picture of Carrizo, but quite a few things need some clarification. Since Carrizo is scheduled for 2015 there is still some time for AMD to apply changes to this design, so the information presented here may or may not resemble the final product.