At the International Solid State Circuits Conference (ISSCC 2015) in San Francisco, AMD (NASDAQ: AMD) unveiled the first architectural details of its Carrizo APU and Excavator core.

The APU, intended for laptops and low-power desktops, is expected to have a formal launch in China this spring but at ISSCC 2015 attendees got a first glimpse at the new silicon.

“As a part of our continued focus on building great products, the advanced power and performance optimizations we have designed into our upcoming ‘Carrizo’ APU will deliver the largest generational performance-per-watt gain ever for a mainstream AMD APU,” Sam Naffziger, AMD Corporate Fellow and co-author of the ISSCC presentation, said in a press release.

Carrizo’s Excavator core is based on the 28nm process, but AMD says that it’s able to squeeze in 29% more transistors on the same die size thanks to something AMD is calling high design libraries. Carrizo has 3.1 billion transistors compared to Haswell-D’s 1.4 billion.

AMD is not yet disclosing the number of Excavator CPU cores in each Carrizo chip. However the company did say that each chip will have eight Radeon GCN cores. AMD also says that Excavator will have a 5% gain in instructions per cycle over Steamroller. Compared to chips with the Steamroller architecture Excavator will have 23% less die area and will consume 40% less power.

Carrizo will also support on-chip H.265 video decode.

As expected, Carrizo chips will support native Heterogeneous System Architecture (HSA) as well as heterogeneous Unified Memory Access (hUMA), which gives the CPU and GPU portions of the SoC the same memory space.

More details on Carrizo will be available this spring, as AMD executives have said before that they intend to do a formal launch of the chip sometime between March to May in China.

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