Just as Intel’s (NASDAQ: INTC) CEO Brian Krzanich opens the regular staff meetings before a dramatically reduced IDF2015 Shenzhen conference, it is a good time to review how government and enterprises don’t see eye to eye when it comes to strategic business.

China’s Tianhe-2 supercomputer is world’s fastest supercomputer, at 33 PFLOPS demonstrated and 55 PFLOPS theoretical performance.

Remember the Tianhe-2 machine at Guangzhou Supercomputer Center, the current World’s number one according to Top 500 Supercomputer list? Unlike some other China supercomputers – Tianhe-2 is fully Intel based machine,  the world’s largest assembly of Intel Xeon CPUs and Xeon Phi accelerators.

Even after Intel ‘opened the kimono’ and gave a nearly 70%  discount on its processors and accelerators, it has given Intel, and therefore US technology sector a major foothold in China and Asian region as such. Over the course of past two years, we were involved in a lot of discussions with Intel staff who were not privy to see the financial impact of the deal — and even argued our undoubtedly solid information. We’re not here to report how things should be, or are in marketing and investor presentations to its numerous staff, but how things really are.

During 2015, the Tianhe-2 supercomputer was supposed to be doubled in its size, up to 110 PFLOPs peak, again using the very same Intel processors and accelerators. Since now these are mature products with lower real manufacturing cost for Intel, they could finally make some real money.

Well, it was not to be: our tweety bird from the window chirped to us that Uncle Sam has put this supercomputer centre, together with National University of Defense Technology in Changsha, the system’s creators, and Tianjin centre, among others, on so a so-called “Denial List”, which prevents any high technology from the USA to be sold to these sites. Our sources used even harsher words.

Knowing that these several sites alone are expected to order some 250+ PFLOPS of compute in the next few years (around 500,000 top-end Broadwell-EP Xeon E5v4 processors, or  approximately $1 billion high margin list price) and they were THE Intel friendly ones, this is quite a loss to Intel, thanks to Uncle Sam.

But, what’s worse strategic loss in time is that, based on this decision as an excuse, indigenous China high end processor architectures can now push the government to gradually remove any dependence on US. This means just one thing: an AMD or Intel x86 processor technology is increasingly becoming errata non grata. Should the Chinese government react in force, it will give the Chinese vendors the blank check support to go all the way a developing their Alpha, POWER and MIPS processors for both the government and the mainstream commercial use.

You may think they are not up to the mark, but remember how fast British ARM architecture became the dominant processing architecture in the world. And this group doesn’t need to worry about the antiquated x86 ISA, worry about satisfying the dumbed down shareholder masses, or overpaying their marketing and sales staff, as well as the fat check, golden parachute-protected CxOs.

They have taken the best that the USA has developed (some of key Alpha, GPGPU and MIPS architects left US over the course of past four years, a lot of them due to non-renewed visas) and discarded due to corporate shenanigans, and the continued developing it much farther than anyone expected both on hardware and software side.

Five years ago, ShenWei showed a CPU that performed faster than the fastest GPUs of the time. Now, fifth generation is approaching, slotting between Tesla and FirePro GPGPUs and next-gen Xeon Phi accelerators. However, this is not an accelerator or a GPGPU – this is a CPU.

So, thanks to Uncle Sam, China might not have a 110 PFLOPS Intel based supercomputer but it definitely will launch a 100 PFLOPS system based on upcoming 64-core, TFLOPS-class ShenWei Alpha, with true blue CPUs possibly faster per socket then even the next generation Xeon Phi or Volta/Pascal-based Teslas.  Next, of course 100 PFLOPS Chinese POWER8 or 9 — (thank you IBM) and then possibly even Loongson MIPS – -it may come back into the high end field with renewed government support because of this Uncle Sam move. All are clean, elegant, scalable high end RISC architectures.

So who are the winners and losers from this?

NUDT and Tianhe may be the losers for now, but only short term. They will simply speed up their HPC ARM plan.

Intel comes out the big loser from this and a lot: who will want to do a phased deployment large x86 machine in China now, and worry about future phases? Then comes Uncle Sam himself: they lost even that little bit of influence on the high end China HPC. How is that for “cutting your nose to spite your face?”.

VR WORLD’s  Analysis: US government moves accelerate the Chinese CPU roadmap while curtailing juiciest sales for Intel and other US vendors.

The post Uncle Sam Shocks Intel With a Ban on Xeon Supercomputers in China appeared first on VR World.

Slides from AMD’s (NASDAQ:AMD) event at the PC Cluster Consortium event in Osaka, Japan offer up details regarding the chip vendor’s roadmap for its GPUs and CPUs, with the takeaways including the launch of a 300W APU targeted at the HPC segment along with the launch of new CPU cores.

At the event, Junji Hayashi, Consumer and Commercial Business Lead at AMD Japan, shared details on the vendor’s K12 ARM as well as the x86 Zen CPU cores. AMD is looking to introduce both ARM as well as traditional x86 cores in a pin compatible platform that is codenamed SkyBridge. Aimed at the server, embedded, semi-custom and client markets, both the ARMv8 and the x86-powered cores will offer 64-bit computing and will be manufactured using a 14-nm FinFET process. SkyBridge will be launching before the end of the year, although an exact launch window was not provided.

The K12 core will feature Simultaneous Multi-Threading, which is a departure from the Clustered Multi-Thread technology that is currently utilized in AMD’s offerings. SMT will offer larger CPU cores the ability to achieve a higher throughput by allocating underutilized resources to an additional, slower, execution thread.

As for GPUs, Hayashi mentioned that AMD would be moving to a two-year release cadence cycle for updating the GPU architecture of APUs. There was also a mention of a High Performance Computing APU, which is said to be radically different from existing designs in that is features the Stacked HBM (High Bandwidth Memory) memory standard. The HPC APUs will slot in between the standard server cores and the FirePro line of cards.

The current generation HBM is nine times faster than GDDR5 memory and 128 times faster than DDR3. AMD is said to be utilizing the same standard in its Radeon 300 series, with the technology itself developed in collaboration with SK Hynix.

The post AMD Reveals Five-Year Roadmap For GPUs and CPUs appeared first on VR World.

Intel (NASDAQ:INTC) has shed further details on its second-generation Xeon Phi CPU, known as Knights Landing.

The processor features several technical achievements, starting with a 14nm manufacturing process, which is a first in this series. Designed to offer high-performance computing, Knights Landing differs from other server-based CPUs in that it uses lots of low-energy cores to run parallel tasks, whereas offerings from IBM (NYSE:IBM) or Oracle (NYSE:ORCL) use fewer but more powerful cores.

Built on Intel’s MIC (Many Integrated Core) architecture with a total of 8 billion transistors, Knights Landing runs a modified version of the Atom Silvermont x86 core in a tile configuration, with a single tile featuring two cores and vector execution units along with shared L2 cache as well as a circuitry that connects the tile to the rest of the mesh network. Intel has mentioned that each Knights Landing package would include a processor with 30 or more tiles and eight on-chip memory modules. Another major highlight with Knights Landing is that it would be able to function as a host processor, meaning that it can boot and run x86 operating systems and application code without any need for recompilation. It can also act as a co-processor.

Talking about memory, the chip vendor has announced that Knights Landing would feature eight 2GB stacks of memory, totaling up to 16GB. The chip is manufactured at Micron, and looks to be a variant of the manufacturer’s Hybrid Memory Cube, which involves stacking memory and using an embedded logic chip to deliver higher bandwidth at a lower power. Micron has mentioned that its HMC modules will be able to transfer data 15 times faster than a standard DDR3 module, while utilizing 70% less energy. Along with on-chip memory, Knights Landing will come with six memory channels that can connect a total of 384GB DDR4 memory.

The result of the new manufacturing process, core design and memory is that Knights Landing will offer three times the performance as the current-gen Knights Corner, with Intel claiming 3 teraflops double-precision and 6 teraflops single-precision performance. That number is close to the 7 teraflops figure Nvidia (NASDAQ:INTC) touted during the launch of its latest video card, the Titan X.

It is no wonder, then, that Intel is aiming for the same use-cases as Nvidia for Knights Landing, with the chip vendor stating that the CPU can be used for deep learning and data analytics. Nvidia, however, has invested significant resources in its platform, and is offering tools such as the Digits software framework. Even if Intel does not manage to successfully challenge Nvidia in the Knights Landing, it is witnessing a great amount of demand, with over 50 companies set to sell server systems with the CPU as the host.

The post Intel Gunning To Challenge Nvidia At HPC With ‘Knights Landing’ Xeon Phi Processor appeared first on VR World.

Japan is a major player in the high performance computing space, but it is often overlooked in favor of discussions about the latest efforts out of China and the US. While China’s national showpiece of Tianhe-2 gets its share of attention, it’s important to remember that on the Linpack Top500 list of HPC systems, within the top 20 Japan holds two positions: the fourth and 15th.

Given Japan’s industrial and scientific might as the world’s third-largest economy, it’s expected that it would also be a major

Professor Satoshi Matsuoka

HPC power. Japanese firms are fast at work designing exascale systems, and the Riken Advanced Institute for Computational Science, home to the world’s fourth fastest supercomputer (which held the title as fastest when it was switched on in 2011), might be home to the world’s first exascale system even before the United States.

On the sidelines of the Supercomputing Frontiers 2015 conference in Singapore, the VR World team sat down with Dr. Satoshi Matsuoka of the Tokyo Institute of Technology, one of the leading figures in HPC in Japan to discuss the state of HPC in the country.

VR World: What is the state of Japanese supercomputing when compared to the competitive landscapes of the United States and China?

Satoshi Matsuoka: Historically, the Japanese HPC market and Japanese technology has always been fairly competitive especially in the system architecture space. US and Japan are now the two countries that are producing supercomputing platforms that are sold worldwide. What China creates is not sold to the outside market.

The Japanese market in computing has always come from the mainframe market. Hitachi, Fujitsu and NEC… they were all mainframe vendors. There were actually others but they have since moved away so there. These have always been the biggest mainframe vendors.

Fujitsu has gone the way of building their own MP piece since actually they built the first MP piece in the 90s, the AP 1000. And then they went to building its own SPARC processors so differs from Oracle, SUN and then now with the K computer [the world’s fourth fastest supercomputer].

VRW: So you would say the Fujitsu SPARC in terms of computational performance, stability for HPC, or client computing is actually ahead of Oracle’s at this point?

SM: Way ahead, yes; it is very HPC focused. So it is hard to say which one is better but for HPC, definitely Fujitsu’s [system] is better. Now looking at the hardware side, there are some advantages [over Oracle], because the Japanese vendors are focusing on building fairly special-purpose HPC hardware. They can really tailor the processors to be directed towards this specific market.

For example, the FX 100; the latest chip from Fujitsu has 34 cores.

VRW: Are you comfortable Fujitsu will continue in the medium to long-term. Are they committed to leading the industry in your mind?

SM:  Yes. They are. They have embedded the Tofu network into the latest FX 100. They were the first adopters of using HMC, the 3D stacking technology. And also they have enormously high injection bandwidth within the network, they also have RAS features [reliability, availability, and serviceability] that are extensive which makes them, in comparison to other processors, really competitive.

So it is becoming increasingly difficult for the Japanese HPC vendors to try to compete with the American counterparts because now designing these processors has become increasingly expensive. There are more transistors, now with lithography design becoming more complicated and you need more validation testing. So much of the Japanese HPC development is being funded by public money because still there are some centers that buy [the HPC systems] and also there are national projects like the K computer now post K computer project has been approved.

So this makes it very hard for the Japanese vendors. Now of course the Japanese vendors also have their own XV-6 line and so forth – Fujitsu sells XV-6 machines; so does NEC, so does Hitachi. And Hitachi has alliance with IBM now so they don’t make their own processors anymore. They work with IBM to design high-end systems.

I think the only way the Japanese vendors can survive is to – but it is my personal view – they will become more aligned with the overall, commoditization leveraging of the other markets. It is not to say they will produce something cheap. Again I will say that commoditization is about building cheap stuff. Commoditization is actually to apply the latest and greatest technologies however to be compliant with certain standards.

VRW: Thanks for your time. 

This interview has been edited and condensed. 

The post Satoshi Matsuoka Interview on state of Japan’s HPC Market appeared first on VR World.

The next big leap in scientific computing is the race to exascale, the capability for a computer to perform 1 million trillion floating-point operations per second.

The US Department of Energy, which will fund the development of such systems, has set targets of what it wants from exascale systems. It wants one available by 2018-2022 and to consume less than 20 megawatts of power.

For scientific computing having this much processing power available would mean that researchers could tackle the next big questions in science. It has been likened to the Hubble telescope, and the advantages it offered scientists in seeing far-off previously invisible stars.

But the problem is current technology is not at the level to accommodate the requirements of exascale computing. In order to reach exascale, at an efficient power and price point, new architecture will have to be developed that changes the way high performance computers compute and move data. Current generation hardware can not simply be scaled up until it reaches exascale level, the power required would simply be enormous and uneconomical.

While the US has put a great deal of resources into the necessary research required to hit exascale, in the end it may be beaten to exascale by another country.

In order to get a better understanding of what needs to happen before we reach exascale, and to get a perspective on some of the other rising powers in HPC computing, VR World spoke with Oak Ridge National Laboratory’s Jack Dongarra who delivered a keynote at the Supercomputing Frontiers 2015 conference in Singapore on the topic.

VR World: During your keynote you mentioned the ‘exascale challenge’. In your opinion, how do we get there from here? What has to happen?

Jack Dongarra: We can’t use today’s technology to build that exascale machine. It would cost too much money, and the power requirements would be way too much. It would take 30 Tianhe-2 clusters in order to get there. We have to have some way to reduce the power and keep the cost under control.

Today, all of our machines are over-provisioned for floating-point. They have an excess floating-point capability. The real issues are related to data movement. It’s related to bandwidth. For example, you have a chip. And this chip has increasing computing capability — you put more cores on it. Those cores need data, and the data has to come in from the sides. You’ve got area that’s increasing due to the computing capability but the perimeter is not increasing to compensate for it. The number of pins limits the data that can go in. That’s the crisis we have.

That has to change. One way it changes is by doing stacking. 3D stacking is a technology that we have at our disposal now. That will allow much more information flow in a way that makes a lot more sense in terms of increasing bandwidth. We have a mechanism for doing that, so we get increased bandwidth. That bandwidth is going to help reduce [power draw] as we don’t have to move data into the chip.

The other thing that’s going to happen is that photonics is going to take over. The data is going to move not over copper lines but over optical paths. The optical paths reduce the amount of power necessary. So that’s a way to enhance the data movement, and to reduce the power consumption of these processors. The chip gets much more affordable, and we can have a chance at turning that computing capability into realized performance — which is a key thing.

In the US, I think we’ll reach exascale in 2022. 2022 is the point where the money will be in place and it’s a question of money. We could build a machine today, but it it would be too expensive. The current thinking is it will be realizable around 2020, and the US is going to be able to deploy the machine in 2022. The money won’t be in place until then, but the technology will be ready ahead of time.

VRW: What’s your take on vendors’ 3D stacking efforts so far?

JD: It’s great. It has to happen. It’s gotta be that way. It’s a natural way to move. It’s going to be the key thing in terms of performance enhancement in the next few years, and being able to effectively employ that as a device. Things look very positive.

VRW: Over the last few years we’ve witnessed China becoming a rising CPU player, with its domestic Alpha and MIPS-based CPUs. Do you have a feeling that conventional CPU vendors have over complicated things for themselves?

JD: China has an indigenous processor which may or may not come out and be deployed in a high performance machine. There are some rumors that the next big machine would be based on the ShenWei CPU. I can understand the motivation for China wanting a processor, they don’t want to dependent on Western technology for these things. There are some issues here. It’s not going to be on x86 architecture, so software will have to be re-written for this machine. Software is a big deal on these systems, but that can be overcome.

When China does deploy this wide scale, Intel will stand up and take notice. It will be a big thing, now China will be in a position to use their product and not Intel’s product. That becomes a big issue.

VRW: Do you see any emerging powers in the HPC space that are outside the traditional industrial powers of US, Japan, Europe and China?

JD: Things have been dominated by the US, followed by the European Union and Japan. China is a more recent investor in high performance computing. Then there are other countries that claim to be wanting to be involved. Korea is a country that claims to wanting to be involved. They are making noise about buying a big machine. They aren’t going to build a machine — they don’t have the processors — they are going to buy a machine from the US.

India has made claims they want to do something. Again, they aren’t going to make their machine. They are going to purchase one.

VRW: Thanks for your time.

The post Jack Dongarra on the Great Exascale Challenge and Rising HPC Powers appeared first on VR World.

Read VR World’s full interview with Prof. Jack Dongarra here. 

Countries around the world, particularly emerging markets, all would love to have a top 100 supercomputer. Being able to have a supercomputer that ranks in the top 100, or even the top 10, would be a national showpiece – a sign of technological might – and would please many of the country’s politicians.

The United States is the world’s dominate high performance computing power, as it has more supercomputers in the top 500 list than any other single country, but China would like to challenge this hegemony. After all, China has the world’s fastest supercomputer, Tianhe-2 , at the National Supercomputer Center at Sun Yat-sen University in Guangzhou.

But in an exclusive interview with VR World, Dr. Jack Dongarra of Oak Ridge National Laboratory and the University of Tennessee, said that China’s HPC stature may be something of a facade. Tianhe-2, while definitely the world’s fastest supercomputer, is somewhat idle and is not being used to its full capacity.

“The real question is: what are they going to use the machine for. I question, at some level, what the Chinese are doing with these big machines,” Dongarra said. “They are are not using the accelerator part of the machine.” [48,000 Intel Xeon Phi 31S1P Accelerator cards].

“I go visit the computing facilities [in China] – and I’m not saying that they are being used for things that are secret – I’m saying that I don’t know what they are being used for,” he continued.

Dongarra explained that part of the reason why Tianhe-2 is more idle than other top supercomputers is because of the funding model China’s government provides. The government paid for the costs to develop and construct the machine, but not for its operational costs which is not the norm in the scientific computing community.

The additional difficulty might be the machine setup China decided to go with. Intel’s (NASDAQ: INTC) Xeon Phi hasn’t proven itself in ease of use when compared to pure CPU code or accelerated code through GPGPU accelerators such as the Nvidia (NASDAQ: NVDA) Tesla or AMD (NASDAQ: AMD) FirePro S Series.

“They have to come up with some mechanism to pay for it,” Dongarra said. “In scientific computing we don’t pay for computing time. It’s not in the culture of how we do business. A situation where people have to pay for computing time limits the computing time being used.”

The post Jack Dongarra: China Isn’t the Emerging HPC Power You Think It Is appeared first on VR World.

To many people, the floating point–universal number debate is something extraneous: an academic issue that involves computer scientists, engineers, and hardware manufacturers.

But as John Gustafson said during his keynote at the Supercomputing Frontiers 2015 conference on Tuesday, the inaccuracies of floating point estimates have real world implications. They can be deadly both in the real sense  — with missile defense batteries mis-calculating intercept times — or as Gustafson explained they can also lose battles in a virtual sense.

During intense battles in multiplayer games, floating point estimates would give different answers for different players. The calculation of if a players’ shot would be a lethal headshot — or a frustrating miss — would have slightly different answers on different platforms. In order to get reliable, reproducible results in the event of discrepancy the software would need to switch back to integers.

In order to have a better understanding of the benefits of unums, and the challenges of implementing them into hardware, the VR World team spoke with Gustafson on the sidelines of the Supercomputing Frontiers 2015 conference in Singapore to learn more.

The VR World team interviews Dr. Gustafson

VR World: You mentioned in your keynote that the implementation of Unum is challenging — in the words of one unnamed Intel executive ‘you can’t boil the ocean’. Why is this?

John Gustafson: What he’s saying is that you can’t change the world. All you have is IEEE floats. That’s the standard. ‘You can’t add a new number type, that’s not going to happen’ is what he said.

VRW: How would you categorize the feedback you’ve gotten from CPU vendors about implementing unums?

JG: People at AMD also didn’t get it. That was a kind of different opposition. They just didn’t see that I could save them so much power, electricity and bandwidth. Maybe it just looked too ambitious to them.

I’m not worried about what the hardware people think. I know they are going to hate it. They’ll have to build it, re-design circuits and all of that. I’m  more interested in everyone else.

VRW: What’s the cost of keeping the existing floating point system, versus implementing Unums? What’s the cost of transitioning hardware to support this, versus the cost of errors in everyday life?

JG: Remember: everything you can do with floats you can do with Unums. They are a subset. It’s a choice between one or the other; if it were I think it would never get off the ground. But if you can do everything you can do now if you have Unums, and you can also do other things, you can then incrementally work your way into them.

The other thing is right now we have to deal with at least two, or three, different precisions. Half precision is now out there. Nvidia has got the half precision out there in hardware as a native type, and single precision as well as double precision are everywhere. Quad precision is not supported by anyone’s hardware… I keep watching to see if it’s going to pop up.

But we already have to manage two, or three, different sizes.

I say replace it with one. And the hardware will let that slide continuously from all different sizes. It will simplify things so it may be cheaper and smaller on chip to do it that way then to have a bunch of single precision units and double precision units. That’s the way they do it now. They have to build separate hardware. Which is very wasteful.

The post Error-Free Computing: Unums Save Both Real and Virtual Battles appeared first on VR World.

Supercomputing Frontiers 2015 kicks off March 17 in Singapore and computer scientist Jack Dongarra is set to deliver one of the opening keynotes for the event, titled Current Trends in Parallel Numerical Computing and Challenges for the Future.

Dongarra is well known within academic and commercial high performance computing circles within the United States and around the world.

Dongarra did not start his academic career with the intention of numbering among the foremost supercomputer experts and innovators. Enrolling in Chicago State University in the 1960s, Dongarra majored in mathematics which he intended to teach as a subject.

But Dongarra’s career objectives soon changed after he learned about a brilliant machine that took the human error and tedium out of math altogether: the digital computer. While it was still emerging at the time as a proper tool for academia, Dongarra quickly found that 16 x 16 matrices were much harder to solve by hand than with a machine, which could do them effortlessly.
Dongarra became so proficient at programming the computer to do math problems, that he eventually changed his pursuit from mathematics to computing, and went on to get a masters in Computer Science at the Illionois Institute of Technology.

Math and computers were a harmonious mix, and at the prestigious Argonne national lab, Dongarra worked with a group to develop a software library based on the algorithms of computer scientist James Wilkinson, and the result was EISPACK, a highly influential library of matrix solving routines. Funded by the U.S Department of Defense, Dongarra went on to develop LINPACK, a similar library for numerical algebra.

Linpack went on to become a de facto benchmark for computing power, and in 1993, Dongarra began compiling the TOP500 list, which remains the most influential authority on rankings of supercomputers around the world.

Dongarra currently lives in Oak Ridge Tennessee, near the Oak Ridge National Laboratory where he works as a researcher. ORNL is home to Jaguar, the world’s second fastest supercomputer. Dongarra is also a Distinguished Professor in the Department of Electrical Engineering and Computer Science at the University of Tennessee, and director of UT’s Innovative Computing Laboratory.

In the last decade, Dongarra has continued to focus on supercomputers, and more specifically, the future of exascale computing. In 2013, Dongarra received a $1 million dollar grant from the Department of Defense to work on the problem of scaling supercomputers to 1,000+ petaflops of strength.

Seeing the project as vitally important to the understanding and management of weather, climate, and other natural systems, Dongarra has worked to overcome the limitations on traditional computing which prevent them from breaking the 1,000 petaflop barrier.

While exascale computers are not yet possible, that hasn’t stopped Dongarra from planning for the future, and part of his efforts include the Parallel Runtime Scheduling and Execution Controller, or PaRSEC, a project aimed at developing algorithms and solutions to manage exascale computers when they arrive.

The expert that experts consult, arguably nobody is better qualified for the task. After receiving the Association for Computing Machinery (ACM)-Institute for Electrical and Electronics Engineers (IEEE) Computer Society Ken Kennedy Award in 2013, widely renowned “father of the Internet” Vint Cerf said of Dongarra “his innovations have contributed immensely to the steep growth of high-performance computing and its ability to illuminate a wide range of scientific questions facing our society.”

Wayne Davis, dean of the college of Engineering at The University of Tennessee remarked “it is hard to imagine what would have not been discovered without [Dongarra’s] work.”

The post Supercomputing Frontiers 2015 to Feature Acclaimed Researcher Jack Dongarra appeared first on VR World.

Singapore’s Supercomputing Frontiers 2015 conference starts Tuesday in the city-state, putting the regional high performance computing center in the spotlight.

Organised by Singapore’s A*STAR Computational Resource Centre, the conference will provide a vital platform for industry and academic experts to interact and explore the latest global trends and innovations in high performance computing.

Singapore has been a growing regional HPC center for the last decade, and the conference co-insides with the deployment of a 1-2 Petaflop multi-platform machine. This is the first machine of this scale in Singapore, and it’s scheduled to be deployed by the end of this year.

The conference themes include the following:

• Supercomputing applications in domains of critical impact in economic and human terms, and especially those requiring computing resources approaching Exascale;
• Big data science merging with supercomputing with associated issues of I/O, high bandwidth networking, storage, workflows and real time processing;
• Architectural complexity of Exascale systems with special focus on supercomputing interconnects, interconnect topologies and routing, and interplay of interconnect topologies with algorithmic communication patterns for both numerically intensive computations and big data; and
• Any other topic that push the boundaries of supercomputing to exascale and beyond

Jack Dongarra, Thomas Sterling and Satoshi Matsuoka are among the keynote speakers scheduled to present at the event.

The event is sponsored by Singapore’s Nanyang Technological University and the National University of Singapore.

Supercomputing Frontiers is expected to be the largest event of its kind organised in South East Asia, and the completely focused main session without vendor marketing presence adds to the technical and strategic value of the conference.

Supercomputing Frontiers begins Tuesday in Singapore.

The post Supercomputing Frontiers 2015 Singapore Begins March 17 appeared first on VR World.

AMD (NASDAQ:AMD) announced late yesterday that Forrest Norrod, formerly Dell’s VP & GM for Server Platforms would be joining the company to take Lisa Su’s position which she had left vacant after ascending to the position of CEO. That puts him in charge of AMD’s entire Enterprise, Embedded and Semi-Custom business unit (EESC) as well as managing all aspects of strategy, business management, engineering, and sales for AMD’s EESC business.

Forrest Norrod comes from over 10 years of working at Dell and having valuable enterprise and server experience, where AMD needs it most. What will be interesting to see is how he will help shape AMD’s future enterprise and server businesses in ways that will set them up for success, because as it stands right now they are in an awful place in terms of server market share and overall sales. Thankfully for Norrod, AMD is already building ARM server chips and shipping them to customers and is working on new ARM and x86 core IP as well, which should give him and his team even more ammunition, come 2016.

Forrest Norrod – AMD

The truth is that Norrod has a long road ahead of him and there’s no doubt that he’s a qualified person for the job, it also may result in AMD having a closer relationship with Dell and getting more AMD products inside of Dell’s own servers.

After all, AMD currently has quite a good relationship with HP, but that hasn’t been enough to get them serious amounts of enterprise design wins to the point where they could actually gain some market share. It is going to be a very big uphill climb, but it really seems like Su has picked the right man for the job and now we just have to see where it will go from here.

“Forrest is an industry veteran whose strong track record of establishing and growing businesses strengthens our leadership team. Forrest’s unique combination of engineering,” Su said in a press release about the new hire. “Business management and technical expertise at both the chip and system level make him ideally suited to lead AMD into an expanded set of markets where our differentiated technology assets provide a competitive advantage.”

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As we had reported, Nvidia announced very strong preliminary earnings for the fiscal first quarter of 2015, calendar Q1 2014. They were supposed to announce their earnings today, May 8th, however someone had mistakenly sent the preliminary earnings announcement to 100 internal users and they decided to make those figures public to avoid any potential insider trading issues.

In terms of Nvidia’s earnings [NASDAQ:NVDA] themselves, the company reported for their fiscal first quarter of 2015, which is actually the first calendar quarter of 2014, earnings of $136 million on $1.1 billion in revenue, which is down sequentially from the fourth quarter where Nvidia is traditionally their strongest. As a result, it is expected to see that their revenue was down 4% quarter over quarter and profit down the same amount. In fact, it is actually really good to only take a 4% quarter over quarter reduction from your strongest quarter, most companies generally see a much larger decrease because of how big their third and fourth quarters are for their business. So, then, it comes as no surprise that when compared to the same quarter a year ago, Nvidia was actually up 16% in terms of revenue ($954 million last year vs. $1,102 this year) and 85% in terms of profitability, which is HUGE. Nvidia took in $77.9 million in profit in their first quarter last year, compared to $136 million this year which accounts for the 85% GAAP increase. Now, if you look at their non-GAAP EPS, then you’ll see that it is a slightly more moderated 61% increase, but even so, it indicates Nvidia is strong as ever, even with some weaker business units.

GAAP EPS were $0.24, up 85% from $0.13 a year ago and down 4% from $0.25 in the previous quarter, and non-GAAP earnings were $0.29, up 61% from $0.18 and down 9% from $0.32 in the previous quarter. Nvidia also saw their gross margin grow to 54.8 % from the previous quarter’s 54.1 % to the same quarter a year ago’s 54.3.

Nvidia Quarterly Revenue by Business Unit

As you can see above, Nvidia’s revenue in their GPU business was actually down quarter over quarter, considering the seasonality of GPU sales, but still up 14% year over year. This is primarily because of Nvidia’s renewed strength in their mobile GPU business in laptops where they saw their strongest marketshare since 2010.  They also saw some renewed strength in their Tegra processor division, which saw growth thanks to their automotive design wins which are now shipping inside Audi’s vehicles. This is combined with Nvidia’s continued strength in their Quadro and Tesla business which has continually buoyed the company’s profitability for the past few years and appears to continue to do so, but to a lesser degree this quarter. Overall revenue was up 16% year over year, meaning that Nvidia continues to improve their strength especially with their high-end products where they saw growth as high as 50%. And even though notebook sales and volumes went down, Nvidia still saw growth in their side of the business, selling the dedicated GPU.

The good thing for Nvidia is that they’ve diversified the placement of their Tegra business with smartphones, tablets and automotive. For their competitors, who are more mobile-heavy, they are experiencing much better growth in their mobile business because of their exposure in automotive in addition to tablets and smartphones. Even though, realistically, Nvidia is still needing a lot of help with their smartphone design wins when compared to their competitors. Perhaps, with Tegra K1 they will get much better pull with Tegra than they did with the Tegra 4 SoC.

Nvidia’s outlook for the next quarter are effectively flat in Q2, in terms of both revenue and operating expenses. As a result of today’s announcements and the company’s outlook, the shares of NVDA are actually trading down 3%, which is disappointing considering the fact that their outlook isn’t necessarily bad and they weren’t necessarily doing poorly.

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Last week ARM invited a group of journalists and analysts to Austin Texas to hear about their server, mobile, and wearable developments. ARM and their partners presented in-depth explanations of their version of the ARM architecture.

On the first day of the conference, HP’s Dwight Barron gave an overview of their Moonshot system.  They have been refining the specifications since its late 2009 inauguration.

Moonshot’s design differs from the traditional servers which have been the general-purpose workhorses of the data center. These boxes have proved to be jacks-of-all-trades, able to run operations for organizations of every shape and size. They started with proprietary operating systems and a warehouse sized room with less computing power than today’s smartphones. In the past, one could choose from several operating systems and server architectures. Today, operating system options are limited and most run on the Intel x86 architecture.

Barron explained that the cloud and mobile applications have changed the assumptions of traditional IT departments. Now IT has to balance rack space density, power consumption, thermal efficiency, and costs. Power is one of the major controlling factors in the data center.

The cloud uses more power than Japan.

The microserver SoC (System on a Chip) typically has a TDP (Thermal Design Power) of 15 to 20 Watts or below, compared to 90 plus Watts for a high-end server. The microserver chassis has the circuitry related to networking, storage, and cluster communications along with integrated cooling and power supply. Thus, the shared resources reduce the complexity of the overall design.

Barron showed a typical dual processor, HPC server motherboard versus the SoC based Server motherboard. The dual processor general purpose motherboard requires system RAM for the processors, dual GPU’s with their RAM as well as the overhead of a PCIe switch, storage controller, and NICs. Each of those separate chipsets consumes power and creates heat. The SoC server motherboard starts with an integrated die having all those features in silicon, which greatly reduces required power and significantly decreases heat. The SoC cartridge and the Moonshot integration will reduce the latency of the wires between the traditional HPC server’s sub-systems.

New era app focused silicon

To prove that Moonshot is a viable approach, HP put in a production configuration. At the HP.COM website there are approximately 100 applications for browsing and downloads. HP.COM’s website gets approximately 300 million hits per day. It was running on 46 HP legacy servers consuming just over 115,000 Watts per day. Replacing that legacy configuration with six Moonshot systems lowered the power consumption to 6,000 Watts and reduced the rack space usage by 89 percent.

HP 300m hits 94% less power

Barron gave a lengthy explanation of why mobile users and cloud services require application focused silicon for the servers. HP will offer server cartridges from multiple vendors – AMD, Applied Micro, Intel, and Texas Instruments. Applied Micro and Texas Instruments are based on the ARM architecture. This provides customers with the option of picking a server cartridge tailored for specific services, like High Performance Computing (HPC), gaming, telecommunications, finance, seismic imaging, Big Data analysis, web serving, and video analysis, to name a few.

TI  has developed hybrid ARM processors that mix anywhere from one to four Cortex-A15 (32-bit) cores with one to eight TMS320C66x digital signal processors into a single SoC. These combinations in the Moonshot can be used in application specific work such as pure cloud infrastructure workloads – servers, switches, routers, network control planes, and telecommunication switches with applications such as VoIP and LTE.

Applied Micro’s X-Gene 1 eight core SoC with ECC (error-correcting code) memory. The platform is capable of running a full LAMP (Linux, Apache, MySQL and PHP) software stack. The X-Gene implements the ARMv8 ISA which is a full 64-bit architecture that is backwards compatible with 32-bit ARMv7. The CPU features hardware virtualization acceleration, MMU virtualization, and advanced SIMD instructions.

Barron said that ARM architecture and HP’s Moonshot will bring new performance levels and reduced power consumption to the data centers.

There was an interesting announcement in last Friday’s Digitimes. “Foxconn Electronics (Hon Hai Precision Industry) and Hewlett-Packard (HP) will establish a joint venture specifically for producing servers for cloud computing and offering related supporting services, according to Foxconn.”
“The partnership reflects innovation in HP’s server business model through combining Foxconn’s R&D capability and manufacturing expertise, with HP’s market leadership in cloud computing products and related services to enable both companies to offer cloud computing solutions which will change existing market game-playing rules, HP CEO Meg Whitman said.”

Paul Teich, CTO and Senior Analyst, Moor Insights & Strategy, said, “HP and Foxconn’s partnership should help both of them address substantial challenges in continuing cloud computing R&D investment in spite of purchasing pressures that might lead to a ‘race to the bottom’ for prices and margins.”

BSN is planning a hands-on evaluation of the performance of an HP Moonshot with the Applied Micro X-gene cartridge. We will let you know the results as we did with our May 2011 comparison of ARM to x86.

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