Just as Intel’s (NASDAQ: INTC) CEO Brian Krzanich opens the regular staff meetings before a dramatically reduced IDF2015 Shenzhen conference, it is a good time to review how government and enterprises don’t see eye to eye when it comes to strategic business.

China’s Tianhe-2 supercomputer is world’s fastest supercomputer, at 33 PFLOPS demonstrated and 55 PFLOPS theoretical performance.

Remember the Tianhe-2 machine at Guangzhou Supercomputer Center, the current World’s number one according to Top 500 Supercomputer list? Unlike some other China supercomputers – Tianhe-2 is fully Intel based machine,  the world’s largest assembly of Intel Xeon CPUs and Xeon Phi accelerators.

Even after Intel ‘opened the kimono’ and gave a nearly 70%  discount on its processors and accelerators, it has given Intel, and therefore US technology sector a major foothold in China and Asian region as such. Over the course of past two years, we were involved in a lot of discussions with Intel staff who were not privy to see the financial impact of the deal — and even argued our undoubtedly solid information. We’re not here to report how things should be, or are in marketing and investor presentations to its numerous staff, but how things really are.

During 2015, the Tianhe-2 supercomputer was supposed to be doubled in its size, up to 110 PFLOPs peak, again using the very same Intel processors and accelerators. Since now these are mature products with lower real manufacturing cost for Intel, they could finally make some real money.

Well, it was not to be: our tweety bird from the window chirped to us that Uncle Sam has put this supercomputer centre, together with National University of Defense Technology in Changsha, the system’s creators, and Tianjin centre, among others, on so a so-called “Denial List”, which prevents any high technology from the USA to be sold to these sites. Our sources used even harsher words.

Knowing that these several sites alone are expected to order some 250+ PFLOPS of compute in the next few years (around 500,000 top-end Broadwell-EP Xeon E5v4 processors, or  approximately $1 billion high margin list price) and they were THE Intel friendly ones, this is quite a loss to Intel, thanks to Uncle Sam.

But, what’s worse strategic loss in time is that, based on this decision as an excuse, indigenous China high end processor architectures can now push the government to gradually remove any dependence on US. This means just one thing: an AMD or Intel x86 processor technology is increasingly becoming errata non grata. Should the Chinese government react in force, it will give the Chinese vendors the blank check support to go all the way a developing their Alpha, POWER and MIPS processors for both the government and the mainstream commercial use.

You may think they are not up to the mark, but remember how fast British ARM architecture became the dominant processing architecture in the world. And this group doesn’t need to worry about the antiquated x86 ISA, worry about satisfying the dumbed down shareholder masses, or overpaying their marketing and sales staff, as well as the fat check, golden parachute-protected CxOs.

They have taken the best that the USA has developed (some of key Alpha, GPGPU and MIPS architects left US over the course of past four years, a lot of them due to non-renewed visas) and discarded due to corporate shenanigans, and the continued developing it much farther than anyone expected both on hardware and software side.

Five years ago, ShenWei showed a CPU that performed faster than the fastest GPUs of the time. Now, fifth generation is approaching, slotting between Tesla and FirePro GPGPUs and next-gen Xeon Phi accelerators. However, this is not an accelerator or a GPGPU – this is a CPU.

So, thanks to Uncle Sam, China might not have a 110 PFLOPS Intel based supercomputer but it definitely will launch a 100 PFLOPS system based on upcoming 64-core, TFLOPS-class ShenWei Alpha, with true blue CPUs possibly faster per socket then even the next generation Xeon Phi or Volta/Pascal-based Teslas.  Next, of course 100 PFLOPS Chinese POWER8 or 9 — (thank you IBM) and then possibly even Loongson MIPS – -it may come back into the high end field with renewed government support because of this Uncle Sam move. All are clean, elegant, scalable high end RISC architectures.

So who are the winners and losers from this?

NUDT and Tianhe may be the losers for now, but only short term. They will simply speed up their HPC ARM plan.

Intel comes out the big loser from this and a lot: who will want to do a phased deployment large x86 machine in China now, and worry about future phases? Then comes Uncle Sam himself: they lost even that little bit of influence on the high end China HPC. How is that for “cutting your nose to spite your face?”.

VR WORLD’s  Analysis: US government moves accelerate the Chinese CPU roadmap while curtailing juiciest sales for Intel and other US vendors.

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Imagination Technologies (LON: IMG), the company now in ownership of MIPS’ technologies, has announced a new 64-bit MIPS processor that goes by the name of the MIPS I6400.

The MIPS I6400 is Imagination Technologies’ and MIPS first 64-bit processor and actually one of the few 64-bit processors out there capable of running on a mobile device and run Android. This MIPS I6400 chip joins the MIPS Warrior family of processors which includes the Warrior M-class of entry-level MIPS cores for embedded and microcontroller applications and the Warrior P-class of high-performance MIPS processors. Based upon how Imagination Technologies is placing this new I-class of processors, it appears as though this will sit in the middle ground between the M-class and P-class of MIPS processors.

MIPS I6400 CPU block diagram

Imagination touts the MIPS I6400 as a scalable, highly efficient 64-bit processor that that can be implemented across a very wide range of performance and power limitations and is capable of high frequencies in more aggressive implementations.

Imagination also has hardware multi-threading which they believe results in higher utilization and CPU efficiency. The company states that its simultaneous multi-threaded (SMT) technology will allow for execution of multiple instructions from multiple threads for every clock cycle. The chips also support hardware virtualization, much like the rest of the MIPS Warrior family but the implementation in the MIPS I6400 allows for up to 15 secure/non-secure guests. Imagination is also quick to tout the high security capabilities of the MIPS I6400 as well as the advanced power management which allows for dedicated clock and voltage levels to each core, only waking cores when they’re needed. This chip also supports 128-bit SIMD based upon MIPS’ SIMD which is designed to support a wide variety of 32 and 64-bit integer and floating point data. This is designed to deliver high performance and high throughput for tasks that can properly utilize the efficiency of SIMD execution in data-parallel applications.

MIPS I6400 Benchmark Performance

In the company’s blog about this new MIPS I6400 processor, the company makes some claims regarding 64-bit performance when compared against their competitor (ARM) and the Cortex-A53 64-bit processor. These include a 50% higher CoreMark and 30% higher DMIPS performance, which need to be independently verified. It would also be very interesting to see how these new processors stack up against ARM and Intel mobile chips in JavaScript performance (Sunspider, etc.) but Imagination Technologies has said that they will not release any benchmarks at this time.

Let’s remember, as of right now MIPS is currently natively supported within Android and will be capable of supporting 64-bit Android as well. While this is great for MIPS, it hasn’t necessarily translated into marketshare against ARM in mobile as the company has very few mobile MIPS licensees for the most current family of products. THe company does claim that they already have a multiple licensees across multiple markets but can’t name any names quite yet.

Does Imagination have what it takes?

Imagination Technologies has a lot of uphill work to do with MIPS and this is a clear indication that Imagination Technologies is not letting off the gas pedal with MIPS.

It clearly wants to be competitive with ARM and Intel, and there’s a good chance that it could nab some SoC licensees from current ARM licensees if its 64-bit CPUs are genuinely better than what ARM is currently offering. However, until its claims are substantiated, it will be very hard to really see them as a real competitor to ARM. Right now, most of MIPS consumer-facing processors are in Ingenic’s SoCs while ARM has tons of licensees. MIPS does have other licensees for other platforms including Qualcomm, Broadcom, Cavium and many others in embedded and networking applications. If it can convince some of their embedded customers to look at their MIPS I6400 series processors, they could seriously become a threat to ARM and give them more competition than Intel has managed to do. In fact, they may help ARM licensees gain more favorable licensing terms if they have room to negotiate thanks to the MIPS I6400 (if it really performs as well as they say it does).

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Oracle used the Imagination Summit 2014 in Santa Clara, California to announce their affiliation with Imagination Technologies of the UK. The collaboration is aimed at enhancing Java for embedded applications, including those used for the Internet of Things (IoT) and to optimize Java for the MIPS CPU architecture.

Oracle shared their vision of the Internet of Things at the Imagination Summit 2014

The MIPS32 and MIPS64 systems will gain support through Oracle’s Java Development Kit (JDK) for developing, debugging, and monitoring Java applications. Developers can use Java in various applications including routers, wireless access points, residential gateways, networking equipment, and mobile devices. Krishna Yarlagadda, President of Imagination in North America, indicated that his company is extremely committed to growing the MIPS ecosystem.

Henrik Stahl, Oracle’s VP of Product Management for Java & Internet of Things, appeared on stage at the Imagination Summit 2014

Imagination’s BusBridge 2 Module features an easily configurable, high-performance, low latency MIPS core interface. It is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to quickly integrate a MIPS core into an AHB-based system. AHB is a bus protocol introduced in Advanced Microcontroller Bus Architecture version 2 from ARM.

Imagination’s BusBridge 3 family of synthesizable functional blocks help SoC designers integrate MIPS32 CPU’s into the most popular high performance chip bus hierarchies. The OCP2AXI bridge works to connect the MIPS32 OCP{Open Core Protocol) interface to an AXI system bus while the OCP Splitter, a small, synthesizable function block has an OCP input that expands to two OCP outputs. Downloads and User Guides are available on line. Imagination also provides a MIPS Developer Forum.

Additionally a joint effort between Oracle and Imagination will be aimed at improving Java on systems involving Imagination’s PowerVR graphics, a product for multimedia processing, including 2D and 3D graphics. The PowerVR architecture is based on Tile Based Deferred Rendering (TBDR), in contrast to Immediate Mode Rendering (IMR) used by most graphics engines in the PC and games console worlds.

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