Just as Intel’s (NASDAQ: INTC) CEO Brian Krzanich opens the regular staff meetings before a dramatically reduced IDF2015 Shenzhen conference, it is a good time to review how government and enterprises don’t see eye to eye when it comes to strategic business.

China’s Tianhe-2 supercomputer is world’s fastest supercomputer, at 33 PFLOPS demonstrated and 55 PFLOPS theoretical performance.

Remember the Tianhe-2 machine at Guangzhou Supercomputer Center, the current World’s number one according to Top 500 Supercomputer list? Unlike some other China supercomputers – Tianhe-2 is fully Intel based machine,  the world’s largest assembly of Intel Xeon CPUs and Xeon Phi accelerators.

Even after Intel ‘opened the kimono’ and gave a nearly 70%  discount on its processors and accelerators, it has given Intel, and therefore US technology sector a major foothold in China and Asian region as such. Over the course of past two years, we were involved in a lot of discussions with Intel staff who were not privy to see the financial impact of the deal — and even argued our undoubtedly solid information. We’re not here to report how things should be, or are in marketing and investor presentations to its numerous staff, but how things really are.

During 2015, the Tianhe-2 supercomputer was supposed to be doubled in its size, up to 110 PFLOPs peak, again using the very same Intel processors and accelerators. Since now these are mature products with lower real manufacturing cost for Intel, they could finally make some real money.

Well, it was not to be: our tweety bird from the window chirped to us that Uncle Sam has put this supercomputer centre, together with National University of Defense Technology in Changsha, the system’s creators, and Tianjin centre, among others, on so a so-called “Denial List”, which prevents any high technology from the USA to be sold to these sites. Our sources used even harsher words.

Knowing that these several sites alone are expected to order some 250+ PFLOPS of compute in the next few years (around 500,000 top-end Broadwell-EP Xeon E5v4 processors, or  approximately $1 billion high margin list price) and they were THE Intel friendly ones, this is quite a loss to Intel, thanks to Uncle Sam.

But, what’s worse strategic loss in time is that, based on this decision as an excuse, indigenous China high end processor architectures can now push the government to gradually remove any dependence on US. This means just one thing: an AMD or Intel x86 processor technology is increasingly becoming errata non grata. Should the Chinese government react in force, it will give the Chinese vendors the blank check support to go all the way a developing their Alpha, POWER and MIPS processors for both the government and the mainstream commercial use.

You may think they are not up to the mark, but remember how fast British ARM architecture became the dominant processing architecture in the world. And this group doesn’t need to worry about the antiquated x86 ISA, worry about satisfying the dumbed down shareholder masses, or overpaying their marketing and sales staff, as well as the fat check, golden parachute-protected CxOs.

They have taken the best that the USA has developed (some of key Alpha, GPGPU and MIPS architects left US over the course of past four years, a lot of them due to non-renewed visas) and discarded due to corporate shenanigans, and the continued developing it much farther than anyone expected both on hardware and software side.

Five years ago, ShenWei showed a CPU that performed faster than the fastest GPUs of the time. Now, fifth generation is approaching, slotting between Tesla and FirePro GPGPUs and next-gen Xeon Phi accelerators. However, this is not an accelerator or a GPGPU – this is a CPU.

So, thanks to Uncle Sam, China might not have a 110 PFLOPS Intel based supercomputer but it definitely will launch a 100 PFLOPS system based on upcoming 64-core, TFLOPS-class ShenWei Alpha, with true blue CPUs possibly faster per socket then even the next generation Xeon Phi or Volta/Pascal-based Teslas.  Next, of course 100 PFLOPS Chinese POWER8 or 9 — (thank you IBM) and then possibly even Loongson MIPS – -it may come back into the high end field with renewed government support because of this Uncle Sam move. All are clean, elegant, scalable high end RISC architectures.

So who are the winners and losers from this?

NUDT and Tianhe may be the losers for now, but only short term. They will simply speed up their HPC ARM plan.

Intel comes out the big loser from this and a lot: who will want to do a phased deployment large x86 machine in China now, and worry about future phases? Then comes Uncle Sam himself: they lost even that little bit of influence on the high end China HPC. How is that for “cutting your nose to spite your face?”.

VR WORLD’s  Analysis: US government moves accelerate the Chinese CPU roadmap while curtailing juiciest sales for Intel and other US vendors.

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Modern high end CPUs are pretty fast these days: an Intel Xeon E5v3 (Haswell-EP) can pack up to 18 cores and two thirds of double precision teraflop in floating point power, while the 2015 Shenwei Alpha from China, with upwards of 32 vector-assisted cores per die, will crunch even more numbers per second. On the other hand, the GPUs have accelerated their own compute roadmap, with both Nvidia (NASDAQ: NVDA) and AMD (NYSE: AMD) devices in the 2015 schedule breaking through the 3 teraflop DP ceiling. Of course, both CPUs and GPUs of this generation come with well tuned, high bandwidth memory systems too.

The same of course applies to Intel’s (NASDAQ: INTC) Xeon Phi compute accelerator, with the next years’ Knights Landing 3 TFlop DP version matching nicely to the next generation Broadwell based Xeon E5v4. Knights Landing Xeon Phi, with its 16 GB 3D stacked memory on the package, will bring new levels of low latency ultra high bandwidth in-memory processing capabilities.

But the problems come when trying to connect these CPUs and GPUs together – the PCI Express link, used now in 99% of the cases, drastically impairs the connection, with its maximum 20 GB/s achievable net bandwidth and up to 1 microsecond roundtrip latency, over an order of magnitude slower latency what Intel QPI, AMD HyperTransport or IBM POWER8 peripheral buses and Nvidia NVlink do – and for many short transfers common in HPC, that latency can mean a lot. These other connections enable coherent shared memory between all those CPUs and GPUs, rather than messaging and copying between separate memory spaces.

So, even though the 2015 Knights Landing will still have to rely on PCIe V3 for connection to its Xeon cousins, the 2016 variety could – hopefully – use the far more efficient QPI. They better do, as, by then, the Nvidia “Pascal” GPU generation, the one after Maxwell, will team up with IBM Power8+ and Power9 to use common NVlink for tight, low latency, shared memory connection between IBM CPUs and Nvidia GPUs in computational environs.

Mind you, that need not apply just in some large supercomputers, but even in your own high end Linux workstations. If the speculated OpenPower expansion to China bears fruits soon, and we see an inexpensive Power8+ lookalike from there, with NVlink on board, making high speed heterogeneous yet shared memory ultrafast 20 – 50 TFLOPs workstations will become a reality within a year or so.

However, there’s a company that could have done it all, much earlier – you guessed it right, AMD. Remember HyperTransport, the most faithful follow-on of the Alpha EV7 bus, ahead of QPI and such? Well, why didn’t they put HyperTransport on its Hawaii and later high end GPUs, and let the GPUs coherently share each other’s memory and that of the matching Opteron CPUs? Even CrossFire stuff would operate far, far faster and neater.

It’s not too late for the company, though. If AMD does decide to again (hopefully) produce top end CPUs, and connects them via HyperTransport to its own arrays of GPUs, they could be back in business.

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